PLDs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing design, placement of components onto the PLD to satisfying timing requirements of a system is often the most important and the most challenging. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated placement algorithms in EDA tools perform the time-consuming task of managing and optimizing designs onto physical devices.
When a system has a large number of tight timing requirements standard automated placement algorithms available in off the shelf EDA tools may be incapable of finding a placement solution that satisfies all of the system's timing requirements. Many automated placement algorithms randomly place components onto the PLD. After compilation, if it is discovered that the system design fails its timing requirements, modifications to the placement of components onto the PLD may be made. Current EDA tools, however, require that placement modifications be made after a compilation process by the EDA tools and that the compilation process be run again thereafter. Compilation processes may require hours of time. In order to satisfy timing requirements, several iterations of modifications and compilation may be required before determining how components are to be grouped and where the components are placed on the target device. When multiple iterations are required to find a solution, this translates into several hours of waiting time.
Thus, what is needed is a method and apparatus for extending the capabilities of tools used for designing systems on PLDs to satisfy timing requirements. This improved method and apparatus should reduce the wait time in the compilation process.